TSL3301CL【PDF 5/21 页】IC LINEAR SENSOR ARRAY 8CHIPLED

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TSL3301CL

102 ?1 LINEAR OPTICAL SENSOR ARRAY

WITH ANALOG-TO-DIGITAL CONVERTER

TAOS141 JULY 2011

The LUMENOLOGY r Company

www.taosinc.com

The TSL3301CL contains seven registers as defined in Table 2. Data in these registers may be written to or read

from using the REGWrite and REGRead commands. Three registers control the gain of the analog-to-digital

converters (ADC). Three other registers allow the offset of the system to be adjusted. Together the gain and

offset registers are used to maximize the achievable dynamic range.

Table 2. Register Address Map

ADDRESS

0x00

Left (pixels 033) offset

0x01

Left (pixels 033) gain

0x02

Center (pixels 3467) offset

0x03

Center (pixels 3467) gain

0x04

Right (pixels 68101) offset

0x05

Right (pixels 68101) gain

0x1F

Mode

The offset registers are 8-bit sign-magnitude values and the gain registers are 5-bit values. The programmed

offset correction is applied to the sampled energy, and then the gain is applied. (i.e., the gain will affect the offset

correction.) These registers allow the user to maximize the dynamic range achievable in the given system.

The last register is the mode register. Bits in this register select the sleep mode as well as options for multichip

arrays and production testing. Note that test and multichip options do not apply to the 8-pin packaged device.

Users should always write 0s into the production test and multichip control bits.

0x1F

MODE

SLP

SLP = Sleep Mode:

1 places device into sleep mode

0 places device in normal operating mode

C1, C0 are Reserved (should be written 0)

P2 to P0 are factory test bits (should be written 0)

Figure 1. Mode Register Bit Assignments

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